1. Field of the Invention
The present invention relates to a storage element which consists of a storage capacitor comprising a storage electrode arranged in an insulated fashion over a doped semiconductor layer and connected to a constant voltage, and a selection element which manifest a gate which is connected to a word line and which is arranged in an insulated fashion above the semiconductor layer, and a source zone connected to a bit line, the source zone being oppositely doped and arranged at the surface of the semiconductor layer, wherein the selection element selectively connects the source zone to a surface storage region of the semiconductor layer which is disposed beneath the storage electrode.
2. Description of the Prior Art
Storage elements of the type mentioned above are known, for example, from the "IEEE Journal of Solid-State Circuits", Vol. SC-11, No. 1, February 1976, pp. 58-63, particularly in connection with FIG, 7 thereof. Their method of operation is based on the principle of charge storage with the aid of an inversion layer formed in the storage region at the surface of the semiconductor layer. Two different logic states are thereby characterized by the presence or absence of such an inversion layer.
The selection element, in accordance with this structure, is constructed either in the form of a selection transistor which manifest a drain zone connected to the storage region, arranged in the semiconductor layer on the surface, and being oppositely doped, or the element is constructed in the form of a charge-coupled element which, proceeding from the cited selection transistor, results in the drain zone being omitted, and the storage electrode of the storage capacitor, and hence also the storage region, are displaced to the edge of the gate of the selection element. In the latter case, for example, due to the economic omission of the drain zone, the storage element requires correspondingly less storage area with the same storage capacity.
However, the selection element always serves the purpose of selectively conductively connecting the source zone with the storage region disposed in the semiconductor surface, in dependence upon a control signal which is supplied to the gate of the selection element by way of the word line, in order, during the write-in and read-out of digital information, to render possible charge transfers between the bit line and the storage region.
In storing the "1" logic state, which is characterized by the lack of an inversion layer, there is, however, no thermal equilibrium. In the space charge region which is formed beneath the storage electrode--subjected to a constant voltage--in the storage region of the semiconductor layer, minority carries are constantly thermally generated and migrate to the semiconductor surface and gradually build up an inversion layer at the surface which finally simulates the other logic state. Therefore, a logic "1" written into the storage element, is transferred by the thermal charge carrier generation, which is also designated as dark current influence, into a logic "0". In order to prevent this from happening, the written-in information, after a so-called storage period, must be read, regenerated and read-in again, whereby the storage time is dimensioned so short that the particular written-in logic state is still clearly recognized during the reading operation.